AN970/0102 1/10 AN970 application note spi communication between st7 and eeprom by 8-bit micro application team introduction the goal of this application note is to present a practical example of communication using the spi peripheral of the st7. it shows an easy way of communicating between a st7 microcontroller and a m95xxx spi eeprom. the purpose is to perform, through spi, a write in the memory, followed by a read of the written data. 1
2/10 spi communication between st7 and eeprom 1 st7 / eeprom spi interface this section summarizes the main features of the st7/eeprom spi interface. please refer to the st7 datasheet for more details. the serial peripheral interface (spi) allows full-duplex, synchronous, serial communication between devices. a spi system may consist of a master and several slaves, or of a system in which devices may be either master or slave. there is only one master at any one time. the bus signals are: - the serial clock (sck). - the mosi (master out slave in). - the miso (master in slave out). one more pin, the ss pin (slave select), is needed to select the slave or the master mode for each device. this can be done in hardware or software mode. in this application the st7 is always used as master (ss pin = high level) and configures the eeprom mode through an output. the st7 and spi interface set-up is shown figure 1. during spi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). data are transmitted msb first. the serial clock is used to synchronize the data transfer during a sequence of eight clock pulses. figure 1. st7 and spi interface set-up st7 spi interface eeprom ss sck mosi miso s vcc i/o c q d m95040 2
3/10 spi communication between st7 and eeprom 2 st72264 configuration 2.1 i/o control four pins of the st72264 are used: - the 3 data and clock spi pins (sck, mosi, miso). - an output pin to select and deselect the m95xxx. - ss pin to select master or slave mode. in our application, the output for selecting the m95xxx is pin 3 of port b. it is configured as output push-pull (refer to the datasheet for details). 2.2 spi peripheral 2.2.1 general this peripheral is configured with the spi control register. the output must be enabled (spe = 1). if the ss pin is high (see spicsr), the st72264 can be declared as master by setting the mstr bit. the transmission speed, in master mode, is selected using the spr0, spr1 and spr2 bits. the cpol and cpha bits define the timing characteristics. when the spie bit is set, spi interrupts are enabled (not used in our case). 2.2.2 ss software configuration the ss pin can be fixed by hardware, either connected to vss (for a slave configuration) or to vdd (for a master configuration). but it can also be software driven through the spicsr reg- ister (ssm and ssi bits) : to set the master configuration (as in our case) : ssm=1 and ssi=1 to set the slave configuration: ssm=1 and ssi=0 70 spie spe spr2 mstr cpol cpha spr1 spr0 70 spif wcol ovr modf - sod ssm ssi
4/10 spi communication between st7 and eeprom 2.2.3 baud rates first the communication speed must be chosen. as the clock is given by the master, the user has to configure the baud rate of the st7 spi (spr[2-0] bits in the spicr register). for each cpu frequency, six baud rates are available. if f cpu = 8mhz, the baud rate range is 62.5khz to 2mhz. 2.2.4 clock phase and polarity then the clock polarity and the clock phase have to be chosen. the clock polarity (cpol bit of the spcr register) controls the steady state value of the clock when no data is being transferred. the clock phase (cpha bit of the spcr register) selects on which clock transition the bit cap- ture is made and consequently on which clock transition data is latched. the user must be careful of the fact that some devices do not allow all timing relationships. for instance, the st95040 eeprom device accepts only cpol,cpha = (0,0) or (1,1) configura- tions.
5/10 spi communication between st7 and eeprom 3 m95040 eeprom management and configuration 3.1 main features this is a 4k memory composed of two pages of 2k bytes. all instructions, addresses and data are shifted in and out of the chip msb first. the write protect pin (w ) and the hold pin (h ) are not used in our application (both are high level). 3.2 status register this device has one status register. the bp1 and bp0 bits in the status register can be used to write protect a block of memory. in this application, both bits are cleared, allowing write access to all the memory. the wel bit indicates the status of the write enable latch. the wip bit indicates whether the memory is busy with a write operation. 3.3 instruction set prior to any operation, the device must be selected (ss pin at low level), then an one-byte in- struction code must be sent to the eeprom. the device has a set of 6 instructions (see table 1 instruction set). table 1. instruction set notes: a 8 = 1, upper page selected. a 8 = 0, lower page selected. instruction description instruction format wren set write enable latch 0000 0110 wrdi reset write enable latch 0000 0100 rdsr read status register 0000 0101 wrsr write status register 0000 0001 read read data from memory array 0000 a 8 011 write write data to memory array 0000 a 8 010
6/10 spi communication between st7 and eeprom 4 st7 / eeprom spi protocol the use of the main functions are briefly described below. for a complete description of the protocol, please refer to the m95040 spi eeprom data sheet. write_enable: the memory contains a write enable latch. this latch must be set prior to any write or wrsr operation. byte_write: this function will write up to 16 bytes of data in the eeprom. after the write in- struction, the memory address must be specified before sending data. byte_read: this function reads the memory. after the read instruction, the memory address is specified. to be able to send the data, the eeprom must receive the clock from the master: the st7. this is made by sending a dummy byte. this operation will generate the 8 clock bits needed. the dummy value will not be seen by the eeprom. write_sr: give the proper value to the status register prior to any communication. read_sr: this process is similar to the byte read process. it will be used to check if there is a write in progress (wip bit of the status register). 5 spi communication between an st7 and an eeprom the software included with this application note is only the spi driver. the complete software can be found in the software library in the st internet website. it is of course only an example. it is up to the user to adapt it to his specific application. 5.1 general description the software is a polling spi communication between the st72264 and eeprom. the first part of the software performs to the initialization of the st72264 (core and spi periph- eral) and of the eeprom (value of status register for no protection). then it executes the write cycles. the ?write_loop? writes in the eeprom, the values 0 to 127 at addresses 255 down to 128. the third part executes the read cycles. the ?read_loop? reads the content of the eeprom at addresses 255 down to 128. finally, the software ends in an infinite loop.
7/10 spi communication between st7 and eeprom 5.2 hardware description two components were used for the application: - 1 st72264 mcu - 1 m95040 eeprom figure 2. hardware description ss pin of st72264 is software driven (high state for a master device). the sck pin is connected to the serial clock pin (c) of the e2proms. the mosi pin to the serial input pins (d). the miso pin to the serial output pins (q). s pin of the eeprom is connected to the pb3 output pin of st72264. 5.3 flowcharts the flowchart of the application is presented below ( figure 3. ). q d s v cc v ss c w h st72264 110pf m95040 v cc v cc v ss v cc v ss 1 v cc v ss ss (soft driven) sck pb3 miso mosi v cc
8/10 spi communication between st7 and eeprom figure 3. flowchart: main main initialization write_enable byte_write read_sr write in progress? increment x x at address 255-x end of writing? (x=128) clear x byte_read at address 255-x increment x end of reading? (x=128) end clear x yes no no no yes yes
9/10 spi communication between st7 and eeprom 5.4 use of several eeproms it is possible to communicate with several eeproms. each one is selected in turn. then the same protocol as described before is followed. the main point is to reserve one i/o pin to select each device. a hardware schematic using two devices is given below ( figure 4. ). the selection of the devices is made using the pb2 and pb3 pins. figure 4. hardware schematic for two devices 5.5 software all the source files in assembly code are given in the zip file with this application note. the source files are for guidance only. stmicroelectronics shall not be held liable for any di- rect, indirect or consequential damages with respect to any claims arising from use of this soft- ware. q d s v cc v ss c w h st72264 110pf m95040 v cc v cc v ss v cc v ss 1 v cc v ss ss (soft driven) sck pb3 miso mosi v cc q d s v cc v ss c w h 110pf m95040 v cc v cc v ss v cc pb2
10/10 spi communication between st7 and eeprom the present note which is for guidance only aims at providing customers with information regarding their products in order for them to save time. as a result, stmicroelectronics shall not be held liable for any direct, indirect or consequential damages with respect to any claims arising from the content of such a note and/or the use made by customers of the information contained herein in connection with their products. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com
|
